1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit operable in synchronous mode, and specifically to a synchronous semiconductor integrated circuit including an ECL (Emitter Coupled Logic) circuit as its component and performing inputting and outputting of signals using a clock signal as a synchronizing signal.
More particularly, the present invention relates to a synchronous semiconductor integrated circuit including a bipolar RA (Random Access Memory) or a BiCMOS RAM as its internal circuit.
2. Description of the Related Art
Various types of memories have been developed and put into practice using semiconductor circuit integration technics. Among these memories, there is a high-speed memory referred to as ECL RAM. The ECL RAM includes a pair of emitter-coupled bipolar transistors as its basic memory cell and operates at ECL levels. The ECL RAM usually uses 0 V, or ground potential, as its first power source potential V.sub.CC and uses a negative potential of -4.5 V or -5.2 V as its second power source potential V.sub.EE. Of the ECL levels, the high level ("H") is about -0.9 V and the low level ("L") is about -1.7 V.
FIG. 1 is a diagram schematically showing an overall arrangement of a conventional semiconductor memory comprising, for example, an ECL RAM. Referring to FIG. 1, the semiconductor memory 7 includes a memory cell array 4 with memory cells arranged in a matrix of rows and columns. The memory cell array 4 includes a plurality of word lines arranged along the rows and a plurality of bit lines arranged along columns. A column of an ECL RAM in general is made of a pair of bit lines and one memory cell is located at each intersection of the pairs of bit lines and word lines.
In order to select a desired memory cell from the memory cell array 4, there are provided an X address buffer decoder 2 and a Y address buffer decoder 3. The X address buffer decoder 2 buffers an X address externally supplied thereto, generates an internal row address and decodes the internal row address, thereby selecting a corresponding word line from the memory cell array 4. The Y address buffer decoder 3 buffers a Y address externally supplied thereto, generates an internal column address and decodes the internal column address, thereby selecting a column (a pair of bit lines) when the memory is of "x 1 bit" arrangement.
The semiconductor memory further includes an R/W control circuit 1, a sense amplifier 5, and a data output buffer 6. The R/W control circuit 1 is supplied with a chip-select signal CS, a write enable signal WE, and input data Din, and in data writing, it writes the data corresponding to the input data Din into a selected memory cell of the memory cell array 4 while disabling the sense amplifier 5. The R/W control circuit 1 also controls the operation of the data output buffer 6 in response to the chip-select signal CS and write-enable signal WE.
The sense amplifier 5 senses and amplifies the data in a memory cell selected from the memory cell array 4 and transmits the data to the data output buffer 6. The data output buffer 6, controlled by a control signal from the R/W control circuit 1, provides output data Dout corresponding to the signal transmitted from the sense amplifier 5. The operation will be briefly described below.
When the chip-select signal CS is in an inactivation state at "H", the R/W control circuit 1 and data output buffer 6 are put into a disable state, where writing and reading of data are inhibited. At this time, the output data Dout delivered from the data output buffer 6 is brought to a predetermined level, for example, at "L", or a high impedance state.
When the chip-select signal CS is turned into an activation state at "L", the X address buffer decoder 2 and the Y address buffer decoder 3, respectively, accept and decode external X address and Y address and generate a row select signal and a column select signal. The memory cell at the intersection of the row and column designated by the row and column select signals is selected.
When the write-enable signal WE is at "H" level, a data-read mode is designated. At this time, the R/W control circuit 1 puts the sense amplifier 5 and data output buffer 6 into an activated state. The activated sense amplifier 5 senses and amplifies the data in the selected memory cell and transmits the data to the data output buffer 6. The data output buffer 6 outputs the output data Dout corresponding to the transmitted data from the sense amplifier 5.
When the write-enable signal WE is at "L", a data-write mode is designated. At this time, the R/W control circuit 1 put the sense amplifier 5 into an inactivated state and at the same time put the data output buffer 6 into an output disable state, thereby setting its output data Dout to a fixed level.
Meanwhile, the R/W control circuit 1, responding to the signals CS and WE, generates internal data from the input signal Din and write the internal data into the selected memory cell. The internal data is generated from the externally supplied input signal Din when the writeenable signal WE is brought to the activation state at "L".
Writing and sensing of data in the ECL RAM are performed according to a current value of the current flowing through the selected column (pair of bit lines). The R/W control circuit 1 applies a signal corresponding to the input signal Din to the bases of the bipolar transistors for writing provided for each bit line, whereby a change of the current corresponding to the input data is produced in the selected column and writing of the data into the memory cell is achieved.
The semiconductor memory of the above described ECL RAM or the like is frequently used in combination with a logic circuit. In such a case, to achieve high-speed and accurate data inputting and outputting, it is preferred to synchronize the logical operation of the logic circuit with write/read operation in the semiconductor memory. In consideration of such situation, a synchronous RAM, i.e., a self-timed RAM (hereinafter briefly called "STRAM"), in which input and output of signals are controlled according to a clock signal used as a synchronizing signal is developed.
FIG. 2 is a block diagram schematically showing the basic circuit configuration of such STRAM. Referring to FIG. 2, the STRAM is integrated on a chip 900, and it includes a standard RAM circuit block 7 having the same structure as that of the RAM shown in FIG. 1, and it also includes an input data retaining circuit 8, a clock signal generator 9, a write pulse generating circuit 10 and an output data retaining circuit 11, for performing data inputting to and data outputting from the standard RAM circuit block 7.
The clock generator 9 buffers an externally supplied clock signal (for example, system clock) CLK and generates an internal clock signal.
The input data retaining circuit 8 receives the clock signal from the clock generator 9 at its clock input CLOCK, latches input signals (address ADD, input data Din, chip-select signal CS, and write-enable signal WE) supplied to its input terminal D, and outputs these signals from its output terminal Q in response to the clock signal.
The write pulse generating circuit 10 generates a write pulse for controlling data writing in response to the internal clock signal from the clock generator 9 and the internal control signals (generated in response to the signals CS and WE) from the input data retaining circuit 8. The write pulse is a pulse signal having the pulse width corresponding to the period that the write-enable signal WE is held in an activation state in the RAM shown in FIG. 1.
The output data retaining circuit 11 receives the internal clock signal from the clock generator 9 at its clock input CLOCK, latches the data from the standard RAM circuit block 7 received at its input terminal D outputs the output data Dout from its output terminal Q in response to the internal clock signal.
The STRAM shown in FIG. 2 differs from the standard RAM shown in FIG. 1 in that its write operation is not started by the signals CS and WE, but started by the clock signal CLK and that the write pulse is generated by the write pulse generating circuit 10 within the chip 900.
FIG. 3 is a block diagram showing in more detail the circuit configuration of the STRAM shown in FIG. 2.
Referring to FIG. 3, the input data retaining circuit 8 includes a retaining circuit 8a which latches and outputs an externally applied address signal ADD (which includes both X address and Y address), a retaining circuit 8b which latches and outputs an externally applied input signal Din, a retaining circuit 8c which latches and outputs the externally applied write-enable signal WE, and a retaining circuit 8d which latches and outputs the externally applied chip select signal CS.
Each of the retaining circuits 8a to 8d is formed of a master-slave register which is triggered at an edge of the internal clock signal. More specifically, the retaining circuit 8a is formed of a master circuit 14a and a slave circuit 15a which receives Q output from the master circuit 14a. The retaining circuit 8b includes a master circuit 14b and a slave circuit 15b which receives Q output from the master circuit 14b. The retaining circuit 8c includes a master circuit 14c and a slave circuit 15c. The retaining circuit 8d includes a master circuit 14d and a slave circuit 15d.
Each of the master circuits 14a to 14d latches a signal applied to the D input at the leading edge of the internal clock signal from the clock generator 9. Each of the slave circuits 15a to 15d latches the signal supplied from its corresponding master circuit at the trailing edge of the internal clock signal.
The write pulse generating circuit 10 is driven by the clock signal from the clock signal generator 9 and generates, at predetermined timings in response to the signals (corresponding to the signals WE and CS from the retaining circuits 8c and 8d), various pulse signals necessary for data writing, which pulse signals control the operations of the sense amplifier and R/W control circuit 1 included in the standard RAM circuit block 7.
The output data retaining circuit 11 is formed of a master-slave register similarly to the input data retaining circuit 8, and includes a master circuit 79 which latches the signal applied to its D input in response to the rising of the internal clock signal from the clock generator 9, and a slave circuit 80 which latches the Q output of the master circuit 79 in response to the falling of the internal clock signal from the clock generator 9. The output from the output data retaining circuit 11 is supplied to an output buffer 13. The output buffer 13, in response to an output from the output data retaining circuit 11, drives an output signal line at a high speed and outputs an output data Dout.
The STRAM further includes a multiplex circuit 12. The standard RAM 7 shown in FIG. 1 controls the output state of the data output buffer 6 by means of the R/W control circuit 1. In the STRAM, however, an read out data signal is transmitted to the output buffer circuit 13 through the output data retaining circuit 11 performing a clocked operation. In this way, the operation of the output buffer circuit 13 is not controlled by an R/W control circuit, and the output state of the output buffer circuit 13 is essentially controlled by the multiplex circuit 12.
The multiplex circuit 12, depending on the operating mode of the STRAM, selectively supplies either of the output data from the standard RAM circuit block 7 and data generated from the signals transmitted from the input data retaining circuits 8c and 8d to the output data retaining circuit 11.
In the data-write operation (when both the signals CS and WE are in the activation state) and at the chip-unselect period (when the signal CS is in the inactivation state), the multiplex circuit 12 supplies a signal at a fixed level of, for example, "L", to the output data retaining circuit 11. When the signal WE is in the inactivation state and the signal CS is in the activation state whereby the data-read operation is indicated, the multiplex circuit 12 transmits the signal sensed and amplified by the sense amplifier of the standard RAM circuit block 7 to the output data retaining circuit 11.
The register type STRAM shown in FIG. 3 has master-slave registers triggered by the edges of the internal clock signal as its signal input and output circuits and, although a read out data is output with a delay of one clock cycle, it has such an advantage that its cycle time can be made essentially shorter than that in the standard RAM because valid data is output in response to the rising of the clock signal. The data-read operation will be described below with reference to FIG. 4
The master circuits 14a to 14d and 79 are brought into a latch state when the clock signal CLK is at "H" and into a through state when the clock signal CLK is at "L". The slave circuits 15a to 15d and 80 are brought into the through state when the clock signal CLK is at "H" and into the latch state when the clock signal CLK is at "L". Here, the latch state means a state that a circuit continuously retains a latched signal and outputs the signal regardless of the kind of the input signal. The through state means a state that a circuit allows an applied input signal to unchangedly pass therethrough. Signals latched by the master circuits 14a to 14d and 79 are the input signals which have already been provided thereto before the clock signal CLK rises to "H". The signals latched by the slave circuits 15a to 15d and 80 are the signals which have already been given thereto before the clock signal CLK falls to " L".
In the data-read operation, the chip-select signal CS is set to "L" and the write-enable signal WE is set to "H". An external address ADD is set to the values designating a desired memory cell. When a time ts elapsed after signals CS, WE, and ADD were settled, the clock signal CLK rises to "H". Here, the time t.sub.s is called a setup time and each signal must be in the settled state when this time has passed. The signals CS, WE, and ADD are required to be held unchanged at least for a period t.sub.H after the rise to "H" of the clock signal CLK. The period t.sub.H is called a hold time. Throughout the periods of the setup time t.sub.S and the hold time t.sub.S, each signal CS, WE, and ADD remains in the settled state.
With the rise to "H" of the clock signal CLK, the internal clock signal from the clock generator 9 also rises to "H". The master circuits 14a to 14d and 79 are thereby brought into the latch state. At this time, since the signals WE, CE, and ADD are already settled in specific states, the signals latched by the master 14a to 14d and 79 are the signals which have already been given thereto before the clock signals CLK rises to "H".
On the other hand, in response to the rise to "H" of the clock signal CLK, the slave circuits 15a to 15d and 80 are brought into the through state. Therefore in response to the rise to "H" of the clock signal CLK, the signals which have been given are transmitted through the slave circuits to their associated circuits.
When the clock signal CLK falls to "L", the slave circuits 15a and 15d and 80 are brought into latch state and the master circuits 14a to 14d are brought into the through state. With the fall to "L" of the clock signal CLK, the addresses transmitted to the X decoder and Y decoder are brought into their settled state, whereby the selected row and selected column are made definite and a corresponding memory cell is selected from the memory cell array.
The write pulse generating circuit 10 generates a one-shot pulse signal in response to the rise of the internal clock signal and supplies a control signal obtained through the logical product of this one-shot pulse signal and the signal WE to the R/W control circuit of the block 7 as the write pulse. In response to this control signal from the write pulse generating circuit 10, the R/W control circuit within the standard RAM circuit block 7 is operated to activate the sense amplifier and, at the same time, ignore an input data from the input data retaining circuit 8. By the activated sense amplifier, the data in the memory cell selected by the X decoder and Y decoder is sensed and amplified to be applied to the multiplex circuit 12. The multiplex circuit 12, since the signals from the input data retaining circuits 8c and 8d are indicating the data-read mode, allows the data from the standard RAM circuit block 7 to pass therethrough.
When the data-read operations are successively performed as shown in FIG. 4, the states of the input data retaining circuits 8c and 8d are set so as to continuously indicate the data-read mode, and during these periods, the multiplex circuit 12 successively transmits the output data from the sense amplifier of the standard RAM circuit block 7 to the output data retaining circuit 11. Therefore, at the end of the periods A and B indicated in FIG. 4, the data from a selected memory cell is delivered at the input of the output data retaining circuit 11. At this time, since the master circuit 79 of the output data retaining circuit 11 is in the latch state, the data read out during the preceding cycle is output through the output buffer circuit 13.
Then, upon rising to "H" of the clock signal CLK once again, the master circuits 14a to 14d and 79 are brought to the latch state and the slave circuits 15a to 15d and 80 are brought into the through state, and the above described operations are repeated. As a result, the data read out in the preceding cycle is output as the output data Dout through the master circuit 79 and the slave circuit 80 of the output data retaining circuit 11, and the output buffer circuit 13. The new output data Dout is output with a delay time t.sub.DR after the rise of the clock signal CLK, the delay time being provided by the output data retaining circuit 11 and the output buffer circuit 13. The delay time t.sub.DR is shorter than the pulse width CLK.PWH of the clock signal CLK (the period that the clock signal CLK is at "H"), so that a settled output data Dout is output before the slave circuit 80 of the output data retaining circuit 11 is brought to the latch state.
As described in the foregoing, although memory cell data Qn corresponding to the address An given at the timing of the rise of the clock signal CLK is output during the following clock cycle, there is no address access time (the time required from application of an address signal to appearance of the output data in a settled state) as is present in the standard RAM shown in FIG. 1. Since the output data reaches a settled state with only the delay time t.sub.DR after the rise of the clock signal through the output slave circuit 80 and the output buffer circuit 13, one cycle time t.sub.CYC (READ) can be shortened and high speed data reading can be achieved.
In the data-read cycle, at the timing of the rise to "H" of the clock signal CLK, the chip-select signal CS is set to "L" and the write-enable signal WE is set to "L" and further, an address ADD is settled, and the input data Din to the input data retaining circuit 8b is settled. In this data-write cycle, selection of a memory cell by the X decoder and Y decoder is performed similarly as in the data-read cycle. At this time, the write pulse generating circuit 10 receives signals from the input data retaining circuits 15c and 15d in response to the rise of the clock signal from the clock generator 9 and generates a control signal (write pulse) necessary for data writing at a predetermined timing. Thereupon, the R/W control circuit accepts an input data Din and transmits the data to a selected memory cell, while it brings the sense amplifier into an inactivated state.
On the other hand, the multiplex circuit 12, in response to the state of the signals from the input data retaining circuits 8c and 8d indicating the data-write mode, ignores the output data from the standard RAM circuit block 7 and continuously transmits a signal at a predetermined level (for example, "L" level) produced from these signals to the output data retaining circuit 11.
Therefore, in the write cycle, the data writing is performed within one clock cycle (the period covering the period A and the period B in FIG. 4). The data writing is also performed in synchronization with the clock signal and, hence, CS- or WE- access time is not required. Since it is only required that some particular signals are settled at the timing of the rise of the clock signal CLK, high-speed data writing can be achieved.
In the above case, the decoding timing by the X decoder and Y decoder is not controlled by the clock signal, and the decoding operation is performed in response to received signals, i.e., the decoding operation is performed in response to a settled address. Data writing or data reading in the standard RAM circuit block 7 is performed upon generation of a signal for setting the R/W control circuit in the data-write mode or the dataread mode, the signal being generated by the write pulse generating circuit 10 at predetermined timing in response to the rise of the clock signal CLK.
FIG. 5 is a diagram showing a specific example of a circuit configuration of the input data retaining circuits 8a to 8d shown in FIG. 3. Since the input data retaining circuits 8a to 8d all have the same circuit configuration, the input data retaining circuit 8, and the input master circuit 14 and input slave circuit 15 are representatively shown.
Referring to FIG. 5, the input data retaining circuit includes the input master circuit 14 and the input slave circuit 15 each of which is formed of an ECL circuit. The master circuit 14 and slave circuit 15 of such ECL circuit configuration have, as their operating power sources, a first power source potential Vcc 47 being, for example, ground potential and a second power source potential V.sub.EE 48 being usually set to -5.2 V or -4.5 V.
The master circuit 14 includes three pairs of emitter-coupled npn bipolar transistors 18/19, 26/27, and 20/28.
The npn bipolar transistor 18 has its base supplied with an input signal IN and its collector connected with the first power source potential 47 through a resistor 16. The npn bipolar transistor 19 has its base supplied with a reference potential V.sub.BB and its collector connected with the first power source potential 47 through a resistor 17.
The npn bipolar transistor 26 has its collector connected with the collector of the transistor 19 and its base connected with a constant current source 29 and also connected with the first power source potential 47 through a transistor 22 and a diode 24. The transistor 27 has its collector connected with the collector of the transistor 18 and its base connected with a constant current source 30 and also connected with the first power source potential 47 through a transistor 23 and a diode 25.
The transistor 20 has its collector connected with the emitters in common of the transistors 18/19 and its base supplied with the inverted signal NCLKB of the clock signal from the clock generator 9. The transistor 28 has its collector connected with the emitters in common of the transistors 26/27 and its base supplied with an internal clock signal CLKB from the clock generator 9. The emitters in common of the transistors 20/28 are connected with a constant current source 21.
The master circuit 14 further includes the transistors 22, 23 and the diodes 24, 25 for applying a predetermined voltage to the respective bases of the transistors 26 and 27.
The npn bipolar transistor 22 has its base connected with the collector of the transistor 18 and the collector of the transistor 27 and its collector connected with the first power source potential V.sub.CC 47. The diode 24 has its anode connected with the emitter of the transistor 22 and its cathode connected with the base of the transistor 26. The npn bipolar transistor 23 has its base connected with the collectors of the transistors 26 and 19 and its collector connected with the first power source potential 47. The diode 25 has its anode connected with the emitter of the transistor 23 and its cathode connected with the base of the transistor 27.
The slave circuit 15 includes pairs of emitter coupled npn bipolar transistors 33/34, 41/42, and 35/43. The transistor 33 has its collector connected with the first power source potential 47 through a resistor 31 and its base connected with the base of the transistor 27. The transistor 34 has its collector connected with the first power source potential 47 through a resistor 32 and its base connected with the base of the transistor 26.
The transistor 41 has its collector connected with the collector of the transistor 34 and the base of the transistor 38 and its base connected with the first power source potential 47 through a transistor 37 and a diode 39 and, also, connected with a constant current source 44. The transistor 42 has its collector connected with the base of the transistor 37 and the collector of the transistor 33 and its base connected with the first power source potential 47 through a transistor 38 and a diode 40 and, also, connected with a constant current source 45.
The transistor 35 has its collector connected with the emitters in common of the transistors 33/34 and its base supplied with the internal clock signal CLKB The transistor 43 has its collector connected with the common emitter of the transistors 41/42 and its base supplied with the complimentary internal clock signal NCLKB. The emitters in common of the transistors 35/43 are connected with a constant current source 36. The slave circuit 15 further includes npn bipolar transistors 37 and 38 and diodes 39 and 40. The transistor 37 has its collector connected with the collectors of the transistors 42 and 33, and its emitter connected with an output node NA. The transistor 38 has its collector connected with the first power source potential 47, its base connected with the collectors of the transistors 39 and 34, and its emitter connected with an output node A. The diode 39 has its anode connected with the output node NA and its cathode connected with the base of the transistor 41. The diode 40 has its anode connected with the output node A and its cathode connected with the base of the transistor 42.
The constant current sources 21, 29, 30, 36, 44 and 45 of the master circuit 14 and slave circuit 15 are circuits for keeping the currents at a constant value flowing therethrough into the second power source potential 48. The operation will be described below.
When the clock signal CLK rises to "H", the internal clock signal CLKB from the clock generator 9 is brought to "H" and the complementary internal clock signal NCKLB from the same is brought to "L". Hence, the transistor 20 is turned off and the transistor 28 is turned on. A current I1 flowing through the constant current source 21 is passed through the transistor 28, with no current passed through the transistor 20. Therefore, no switching operation is performed by the transistors 18 and 19. Thus, regardless of the state of the input signal IN, potentials corresponding to the collector potentials of the transistors 18 and 19 at the time of the clock signal CLKB rising to "H" are supplied to the transistors 26 and 27 through the diodes 24 and 25, respectively, so that the transistors 26 and 27 provide current flows corresponding to their base potentials.
When the input signal IN is at a higher level than the reference potential V.sub.BB, the collector potential of the transistor 18 goes to "L" and the collector potential of the transistor 19 goes to "H". These potentials are shifted in level through the transistors 22 and 23 and the diodes 24 and 25 and transmitted to the bases of the transistors 26 and 27. Hence, the base potential of the transistor 26 goes to "L" and the base potential of the transistor 27 goes to "H". In such state, if the clock signal CLKB rises to "H", the current flowing through the resistor 16 and the transistor 18 is switched to flow through the transistor 27, and the current flowing through the resistor 17 and the transistor 19 is switched to flow the transistor 26. Therefore, the states of the transistors 23 and 22 do not change and also the base potentials of the transistors 26 and 27 do not change, so that the input signal which was applied at the time of the rise of the clock signal CLK (CLKB) is latched by the master circuit 14 and transmitted to the slave circuit 15 at the subsequent stage. This is the latch state.
When the clock signal CLK falls to "L", the clock signal CLKB is brought to "L" and the complementary clock signal NCLKB is brought to "H". In this case, the current I1 flowing through the constant current source 21 is allowed to flow through the resistors 16 and 17, the transistors 18 and 19, and the transistor 20, the values of the currents flowing through the transistors 18 and 19 reflecting the relationship between the input signal IN and the reference voltage V.sub.BB. In such state, if the input signal changes, the base potentials of the transistors 22 and 23 are changed and, accordingly, the base potentials of the transistors 26 and 27 are also changed. Such change corresponds to the change in the input signal IN and, thus, the master circuit 14 is brought to the through state where the input signal IN is allowed to unchangedly pass therethrough.
The operation in the slave circuit 15 is quite the same as that in the master circuit 14. When the clock signal CLKB is at "H", a current I2 flowing through the constant current source 36 is allowed to flow through the resistors 31, 32, the transistors 33, 34, and the transistor 35 (the transistor 43 is in the off state), and a signal corresponding to the signal transmitted from the master circuit 14 (the base potentials of the transistors 26 and 27) is output at the output nodes A and NA.
Therefore, in the described state, the slave circuit 15 is in its through state.
On the other hand, when the clock signal CLK falls to "L", the current I2 flowing through the constant current source 36 is turned to flow through the transistors 41, 42, and 42, and the transistors 33 and 34 do not perform the switching operation. Therefore, in this state, the signal corresponding to the signal state at the time of the fall of the clock signal CLKB is continuously output from the output nodes A and NA. This state is the latch state.
Since the transistors in the ECL circuit are not operated in the saturation region but operated in the active region (nonsaturation region) and the "H" and "L" of the signals are determined by the magnitude of the currents flowing therethrough, the diodes 24, 25, 39, and 40 are provided in the circuit as the level shift means so that the transistors can be prevented from having the base-collector paths forwardly biased to be operated in the saturation region.
The constant current sources 29, 30, 44, and 45 are provided so that, even if the transistors 22, 23, 37, and 38 come to have substantially high resistance values depending on their base potentials, constant currents may be flowed against such changed resistance values and potentials corresponding to the input signal may be provided to their associated transistors 26, 27, 41, and 42.
FIG. 6 is a diagram showing an example of a specific configuration of the output data retaining circuit 11 shown in FIG. 3. The output data retaining circuit 11 has the same configuration as that of the input data retaining circuit 8 shown in FIG. 5, only differing therefrom in that the signals supplied to the input transistors 51 and 52 of the output master circuit 79 are complementary DATA and DATA from the sense amplifier in the block 7 and that the output signals from the slave circuit 80 are complementary output data AOUT and NAOUT.
Referring to FIG. 6, the output master circuit 79 includes npn bipolar transistors 51, 52, 53, 55, 56, 59, 60, and 61, resistors 49 and 50, and diodes 57 and 58. The emitter-coupled transistor 51 and 52 are supplied with the DATA and DATA at their bases, respectively.
The slave circuit 80 includes npn bipolar transistors 66, 67, 68, 70, 71, 74, 75, and 76, resistors 64 and 65, and diodes 72 and 73. The emitter-coupled transistors 66 and 67 are supplied with the output signals from the master circuit 79 at their bases. The emitter potentials of the transistors 70 and 71 are output as the output data NAOUT and AOUT.
The operation of the output data retaining circuit 11 shown in FIG. 6, is similar to that of the operation of the input data retaining circuit 8 shown in FIG. 5. When the clock signal CLK rises to "H", the complementary internal clock signal NCLKB is brought to "L" , whereby a current is flowed to the constant current source 54 through the emitter-coupled transistors 59 and 60 and transistors 61, while the switching operation of the input transistors 51 and 52 is inhibited. Hence, this state is the latch state. When the clock signal CLK is brought to "L", the complementary clock signal NCLKB is brought to "H" and the current to the constant current source 54 is allowed to flow through the input transistors 51 and 52 and the transistor 53, and thus, the switching operation according to the input data to the master circuit 79 is performed. Hence, this state is the through state.
Similar operation is performed in the slave circuit 80. When the internal clock signal CLKB is at "H", the circuit is brought into the through state where it allows the output signal from the master circuit 79 to be transmitted unchangedly, and when the internal clock signal CLKB is at "L", the circuit is brought into the latch state where the data previously provided thereto is output regardless of the output of the master circuit 79.
In the course of the above described operation, the period that the external clock signal CLK is at "H" is the period A shown in FIG. 4. Therefore, during the period A, the input master circuit 14 and the output master circuit 79 are in the latch state and the input slave circuit 15 and the output slave circuit 80 are in the through state. On the other hand, during the period that the external clock signal CLK is at "L"(the period B in FIG. 16), the input master circuit 14 and the output master circuit 79 are in the through state and the input slave circuit 15 and the output slave circuit 80 are in the latch state. Therefore, during the periods A and B in the operating waveform diagram of FIG. 4, the data supplied at the timing of the rise of the external clock signal CLK is transmitted through the multiplex circuit 12 so as to reach the input node of the output slave circuit 80 at the end of the period B. The data as the output data is asserted when the delay period t.sub.DR associated with the output data retaining circuit 11 and the output buffer circuit 13 has elapsed after the start of the period C.
Thus, the data-read cycle is started when the external clock signal CLK rises, and the data of the preceding cycle is made valid as the output at the time of this rise of the external clock signal CLK.
Conventional semiconductor integrated circuits have been structured as described above, and the address access time required for the standard RAM, in the case of the STRAM, is expressed as the sum of the clock cycle time (t.sub.CYC (READ) at the time of data reading) and the output delay time t.sub.DR. Therefore, with such circuit, it is possible to perform high-speed data write/read operations.
Generally, such semiconductor integrated circuit is subjected to functional tests to determine whether or not a product is good and capable of performing desired functions.
In such tests, it becomes necessary to measure the access time of the STRAM to determine the maximum and minimum times thereof, and set up time margins for various signals. In measuring such access time of STRAMs, the length of the access time is usually varied even if STRAMs function normally, due to voltage drops in internal signal lines, design factors, fluctuations of characteristics of devices owing to varied process parameters, and the like. When there are differences in the access time, the cycle time must be extended to measure the access time for the bit requiring a longer address access time, that is, the bit having a longer "address access time" in the standard RAM. Thus, there has been a problem that it is not possible to measure the access time of all the STRAMs with a unique clock signal cycle but the cycle time must be changed from device to device and, therefore, it is not possible to quickly measure the access times of the STRAMs.
When the cycle time is changed as described above, it follows that the operating timing of each part is changed and, such a problem arises that the operating conditions of the internal circuits (such a the standard RAM circuit block) may be changed, leading to a problem that accurate functional tests cannot be carried out.
In the stage of the standard RAM circuit blocks arranged on a wafer, measurement of their access times can be performed by means of a probe card (a testing instrument provided with wirings capable of applying desired signals to pads or nodes in a flip-chip state). After they are packaged, however, it becomes necessary to externally apply a clock signal in performing the functional test, and therefore, a problem arises that, when a malfunction is arising at the input/output circuit or the clock circuit or it is arising in the memory cells or peripheral circuitry, it makes difficult to carry out the failure analysis t locate the position of malfunction.
More specifically, the problem is that the analysis to locate the position of malfunction becomes difficult because signals can only be applied to the chip through its pin terminals once it has been packaged.
The above mentioned problems arise not only in STRAMs but also in general synchronous semiconductor circuits having input/output circuits and internal functional circuits with each of such circuits operating in synchronization with a clock signal.
A system externally monitoring a write pulse of a semiconductor memory supporting a built-in write pulse generating circuit is disclosed in Japanese Patent Laying-Open No. 1-184798. Such prior art memory device includes a write pulse generating circuit, a switching circuit responsive to an external control signal for allowing either of the external control signal and the write pulse to pass therethrough, a circuit applying an output pulse of the switching circuit to a memory array as the write pulse, and a circuit for externally monitoring the output of the switching circuit. This prior art is directed only to adjustments of the write pulse.